Équipe de recherche :Research Team:
Secure and Safe Hardware (SSH)Secure and Safe Hardware (SSH)
Laboratoire :Laboratory:
Laboratoire Traitement et Communication de l'Information (LTCI)Information Processing and Communication Laboratory (LTCI)
Département :Department:
Communications et Électronique (Comelec)Communications and Electronics (Comelec)
Alaa Eddine Mazouz joined the SSH team at Télécom Paris on September 1, 2025 as an Associate Professor in Embedded AI. His research focuses on embedded AI, efficient deep learning, and model optimization for resource-constrained systems, with a particular emphasis on FPGAs and reconfigurable hardware. He is also interested in continual learning, online adaptation, neural image compression, and computer vision applications for space systems.
He received his PhD from the University of Surrey, UK, at the Surrey Space Centre, where he worked on online reconfiguration of convolutional neural networks for onboard vision applications. His doctoral research addressed automatic generation of CNN accelerators on FPGAs, on-device training, runtime adaptation, and accuracy-latency-power trade-offs for autonomous embedded systems. He then completed a postdoctoral fellowship at Télécom Paris, within the SSH and C2S teams, working on embedded AI, learned image compression, secure model deployment, and adaptive learning on FPGAs.
Research activities
His research develops algorithms and architectures that make AI models more efficient, adaptive, and deployable on embedded hardware platforms. His main research areas include:
- embedded AI on FPGAs and reconfigurable neural-network accelerators;
- compiler flows, design space exploration, and runtime reconfiguration for CNN accelerators;
- efficient deep learning, model compression, pruning, quantization, and hardware-aware deployment;
- continual and online learning on embedded devices, including progressive adaptation and experience replay;
- neural image and video compression under latency, energy, and resource constraints;
- secure deployment of AI models, including watermarking, quantization-aware watermarking, and encryption;
- computer vision for space systems, onboard perception, and satellite applications.
Projects and funding
- Participation in the Horizon Europe ENFIELD project on Adaptive AI, with activities related to embedded, efficient, and adaptive AI.
- Doctoral research at the Surrey Space Centre in the context of space projects supported by the UK Space Agency and ESA.
- Research collaborations with Télécom Paris, Télécom SudParis, Università di Torino, and academic partners on learned image compression, FPGA deployment, and model security.
Teaching activities
His teaching activities focus on digital design, reconfigurable architectures, HDL languages, embedded AI, and model optimization for constrained hardware platforms.
- C5 SETI – Frugal AI for FPGAs: course coordinator. The course introduces the deployment of neural networks on FPGAs, focusing on compute, memory, latency, and energy constraints. It covers Vitis AI workflows, quantization, pruning, hardware profiling, and accuracy-performance trade-offs.
- ELEC101 / ESAC – Digital Design: teaching in digital systems design, combinational and sequential logic, HDL-based design, and FPGA implementation.
- Reconfigurable Architectures and HDL Language: contribution to teaching on FPGA architectures, HDL programming, and reconfigurable digital circuit design.
- Algorithms and Architectures for Digital Computing: contribution to system synthesis, High-Level Synthesis (HLS), and digital architectures for computing.